This application is based upon and claims priority from prior French Patent Application No. 98-12249, filed Sep. 30, 1998, the entire disclosure of which is herein incorporated by reference.
1. Field of the Invention
The present invention relates to semiconductor circuits, and more specifically to a semiconductor circuit having surface features.
2. Description of Related Art
When fabricating prototype semiconductor circuits and when fabricating semiconductor circuits on a production line, electrical tests are performed to detect and locate possible faults in the structure of the semiconductor circuits being tested. In particular, such faults can include imperfectly produced components and missing or erroneous electrical connections between components. When the position of a fault in the structure is located, there is a need to physically examine the semiconductor component being tested and the discovered fault or faults and, optionally, to carry out a repair.
For this purpose, there are machines that have a chamber into which the tested semiconductor circuit can be placed. Such machines also include tools for carrying out examination and/or intervention operations (such as focused ion beam (FIB) tools and electron beam (EB) testers) to modify or adapt the semiconductor circuit fabrication processes. Additionally, the machines are equipped with an electronic navigation system that allows the operator to produce a topographic record of the projecting parts on the upper surface of the tested semiconductor circuit that result from the final layer of the components of the circuit.
The navigation system can bring the image of this topographic record into coincidence with an image of a reference drawing for this topography that is contained in a database. After producing the image and then superimposing the two images, the operator can adjust the tool with respect to the surface of the semiconductor circuit so as to bring it into a chosen position by taking as a reference that image of the reference drawing associated with the position of the tool. The chosen position typically corresponds to the location of a fault that was discovered during the electrical test.
However, such a procedure has limitations that become more critical as the internal components of the semiconductor circuits are moved closer and closer together. More specifically, if the external surface of the semiconductor layer has projecting parts that are relatively close to each other, the tool can be positioned with relatively high precision. However, if the external surface of the tested semiconductor circuit has projecting parts that are relatively far apart, positioning difficulties are encountered, especially with regard to the orientation of the semiconductor circuit with respect to the reference drawing.
Further, the positioning operation becomes almost impossible when the external surface of the tested semiconductor circuit has few or no projecting parts. For example, memory circuits only rarely have more than just two projecting peripheral strips for the electrical supplies on their external surface. In such a case, it is necessary to use a tool of the machine to bare at least two local parts of an internal layer of the semiconductor circuit (e.g., a metallization layer) in the region of the location that is to be explored by removing the upper layers.
This allows a topographic record of the exposed parts to be made and brought into coincidence with an image of the reference drawing of this internal layer from the database. Then, the tool may be adjusted with respect to the reference drawing in correspondence with the topographic record. During these processes, the operations carried out to position the tool with respect to the external surface of the semiconductor circuit are relatively tedious and can turn out to be imprecise. Thus, any work carried out locally on the tested semiconductor circuit may not be at the proper location and this can lead to an ultimate deterioration of the tested circuit.
In view of these drawbacks, it is an object of the present invention to overcome the above-mentioned drawbacks and to provide a semiconductor circuit and a method of adjusting a tool with respect to the semiconductor circuit to facilitate such adjustment.
One embodiment of the present invention provides a semiconductor circuit that includes components and registration features that are electrically isolated from the components. The registration features form projecting parts that are uniformly distributed in the form of a matrix over at least part of the external surface of the circuit so as to define adjacent registration areas. In a preferred embodiment, the semiconductor circuit also includes metal registration features that are produced in at least one metallization level of the circuit.
Another embodiment of the present invention provides a method of adjusting a tool so as to put it into a particular position with respect to the surface of a semiconductor circuit that has registration features defining adjacent registration areas. According to the method, an at least partial topographic record of the registration features on the surface of the semiconductor circuit is produced, and the registration features of the topographic record are brought into coincidence with reference features of a reference drawing. The reference features of the reference drawing correspond to the registration features of the circuit. The position of the tool is adjusted with respect to at least some of the reference features or registration features. In one preferred method, the registration features form a plurality of projecting parts that are uniformly distributed in the form of a matrix over at least part of the external surface of the circuit so as to define a plurality of adjacent registration areas, and the position of the tool is adjusted with respect to at least some of the adjacent reference or registration features that define the registration area of the circuit in which the position lies.
Other objects, features, and advantages of the present invention will become apparent from the following detailed description. It should be understood, however, that the detailed description and specific examples, while indicating preferred embodiments of the present invention, are given by way of illustration only and various modifications may naturally be performed without deviating from the present invention.